riscv plic中断控制器

plic@c000000 {
	phandle = <0x9>;
	riscv,ndev = <0x35>;       // 这个PLIC支持的中断源数量为53
	reg = <0x0 0xc000000 0x0 0x600000>;     // 0xc000000 - 0xc600000是PLIC的寄存器区域
	interrupts-extended = <0x8 0xb 0x8 0x9 0x6 0xb 0x6 0x9 0x4 0xb 0x4 0x9 0x2 0xb 0x2 0x9>;
	interrupt-controller;
	compatible = "sifive,plic-1.0.0", "riscv,plic0";
	#interrupt-cells = <0x1>;

};

struct plic_priv {
	struct cpumask lmask;   // 可以处理plic中断的cpu集合
	struct irq_domain *irqdomain;   // plic中断控制器对应的中断域
	void __iomem *regs;    // dts中指定的plic寄存器基地址
	unsigned long plic_quirks;   // 中断触发模式(edge/level)
	unsigned int nr_irqs;      // dts中指定的最大中断个数
	unsigned long *prio_save;   // irqs bitmap 存储中断使能状态位
};

struct plic_handler {    // per-cpu变量
	bool			present;
	void __iomem		*hart_base;    // 每个cpu对应的context基地址
	/*
	 * Protect mask operations on the registers given that we can't
	 * assume atomic memory operations work on them.
	 */
	raw_spinlock_t		enable_lock;    // 中断使能并发保护锁
	void __iomem		*enable_base;   // 中断使能寄存器基地址
	u32			*enable_save;  // 中断使能标记位的临时存储（suspend/resume时会用到）
	struct plic_priv	*priv;   // plic私有数据

};

static int __init __plic_init(struct device_node *node,
			      struct device_node *parent,
			      unsigned long plic_quirks)
{
	int error = 0, nr_contexts, nr_handlers = 0, i;
	u32 nr_irqs;
	struct plic_priv *priv;
	struct plic_handler *handler;
	unsigned int cpu;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->plic_quirks = plic_quirks;

	priv->regs = of_iomap(node, 0);
	if (WARN_ON(!priv->regs)) {
		error = -EIO;
		goto out_free_priv;
	}

	error = -EINVAL;
	of_property_read_u32(node, "riscv,ndev", &nr_irqs);
	if (WARN_ON(!nr_irqs))
		goto out_iounmap;

	priv->nr_irqs = nr_irqs;

	priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL);
	if (!priv->prio_save)
		goto out_free_priority_reg;

	nr_contexts = of_irq_count(node);
	if (WARN_ON(!nr_contexts))
		goto out_free_priority_reg;

	error = -ENOMEM;
	priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
			&plic_irqdomain_ops, priv);
	if (WARN_ON(!priv->irqdomain))
		goto out_free_priority_reg;

	for (i = 0; i < nr_contexts; i++) {
		struct of_phandle_args parent;
		irq_hw_number_t hwirq;
		int cpu;
		unsigned long hartid;

		if (of_irq_parse_one(node, i, &parent)) {
			pr_err("failed to parse parent for context %d.\n", i);
			continue;
		}

		/*
		 * Skip contexts other than external interrupts for our
		 * privilege level.
		 */
		if (parent.args[0] != RV_IRQ_EXT) { // 只跟踪记录S模式下的context
			/* Disable S-mode enable bits if running in M-mode. */
			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
				void __iomem *enable_base = priv->regs +
					CONTEXT_ENABLE_BASE +
					i * CONTEXT_ENABLE_SIZE;

				for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
					__plic_toggle(enable_base, hwirq, 0);
			}
			continue;
		}   

		error = riscv_of_parent_hartid(parent.np, &hartid);
		if (error < 0) {
			pr_warn("failed to parse hart ID for context %d.\n", i);
			continue;
		}

		cpu = riscv_hartid_to_cpuid(hartid);
		if (cpu < 0) {
			pr_warn("Invalid cpuid for context %d\n", i);
			continue;
		}

		/* Find parent domain and register chained handler */
		if (!plic_parent_irq && irq_find_host(parent.np)) {
			plic_parent_irq = irq_of_parse_and_map(node, i);
			if (plic_parent_irq)
				irq_set_chained_handler(plic_parent_irq,
							plic_handle_irq);    // 注册plic中断处理函数
		}

		/*
		 * When running in M-mode we need to ignore the S-mode handler.
		 * Here we assume it always comes later, but that might be a
		 * little fragile.
		 */
		handler = per_cpu_ptr(&plic_handlers, cpu);
		if (handler->present) {
			pr_warn("handler already present for context %d.\n", i);
			plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD);
			goto done;
		}

		cpumask_set_cpu(cpu, &priv->lmask); //可以处理plic中断的cpu集合
		handler->present = true;
		handler->hart_base = priv->regs + CONTEXT_BASE +
			i * CONTEXT_SIZE;      // 预先算出 hart S特权模式偏移后对应的context基地址
		raw_spin_lock_init(&handler->enable_lock);
		handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE +
			i * CONTEXT_ENABLE_SIZE;   // 预先算出hart对应的使能寄存器基地址
		handler->priv = priv;

		handler->enable_save =  kcalloc(DIV_ROUND_UP(nr_irqs, 32),
						sizeof(*handler->enable_save), GFP_KERNEL);  // suspend/resume阶段临时存储记录中断使能状态
		if (!handler->enable_save)
			goto out_free_enable_reg;
done:
		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
			plic_toggle(handler, hwirq, 0); // 初始化为关中断
			writel(1, priv->regs + PRIORITY_BASE +
				  hwirq * PRIORITY_PER_ID);// 中断优先级固定为最低优先级1
		}
		nr_handlers++;
	}

	/*
	 * We can have multiple PLIC instances so setup cpuhp state only
	 * when context handler for current/boot CPU is present.
	 */
	handler = this_cpu_ptr(&plic_handlers);
	if (handler->present && !plic_cpuhp_setup_done) {
		cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
				  "irqchip/sifive/plic:starting",
				  plic_starting_cpu, plic_dying_cpu);
		plic_cpuhp_setup_done = true;
	}
	register_syscore_ops(&plic_irq_syscore_ops);

	pr_err("%pOFP: mapped %d interrupts with %d handlers for"
		" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
	return 0;

out_free_enable_reg:
	for_each_cpu(cpu, cpu_present_mask) {
		handler = per_cpu_ptr(&plic_handlers, cpu);
		kfree(handler->enable_save);
	}
out_free_priority_reg:
	kfree(priv->prio_save);
out_iounmap:
	iounmap(priv->regs);
out_free_priv:
	kfree(priv);
	return error;
}

/*
 * Handling an interrupt is a two-step process: first you claim the interrupt
 * by reading the claim register, then you complete the interrupt by writing
 * that source ID back to the same claim register.  This automatically enables
 * and disables the interrupt, so there's nothing else to do.
 */
static void plic_handle_irq(struct irq_desc *desc)
{
	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
	irq_hw_number_t hwirq;

	WARN_ON_ONCE(!handler->present);

	chained_irq_enter(chip, desc);

	while ((hwirq = readl(claim))) {
		int err = generic_handle_domain_irq(handler->priv->irqdomain,
						    hwirq);
		if (unlikely(err))
			pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
					hwirq);
	}

	chained_irq_exit(chip, desc);
}

struct irq_common_data {
	......
	cpumask_var_t 	smp_affinity    // IRQ affinity on SMP. If this is an IPI related irq, then this is the mask of the CPUs to which an IPI can be sent.
	cpumask_var_t	effective_affinity  // The effective IRQ affinity on SMP as some irq chips do not allow multi CPU destinations. A subset of affinity.
	.......
}

static int plic_set_affinity(struct irq_data *d,
			     const struct cpumask *mask_val, bool force)
{
	unsigned int cpu;
	struct cpumask amask;
	struct plic_priv *priv = irq_data_get_irq_chip_data(d);

	cpumask_and(&amask, &priv->lmask, mask_val); // amask为参数指定的cpu集合和plic支持处理该中断的cpu集合的交集

	// 这里可以看到有效掩码中只会包含一个固定cpu
	if (force)
		cpu = cpumask_first(&amask);
	else
		cpu = cpumask_any_and(&amask, cpu_online_mask);

	if (cpu >= nr_cpu_ids)
		return -EINVAL;

	plic_irq_disable(d);   // 关闭旧的有效掩码的cpu对应的irq中断

	irq_data_update_effective_affinity(d, cpumask_of(cpu)); // 更新有效掩码

	if (!irqd_irq_disabled(d))  // 如果cpu侧没有禁止该中断
		plic_irq_enable(d);  // 打开新的有效掩码的cpu对应的irq中断

	return IRQ_SET_MASK_OK_DONE;
}

static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
{
	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);  // 使能
	u32 hwirq_mask = 1 << (hwirq % 32);

	if (enable)
		writel(readl(reg) | hwirq_mask, reg);
	else
		writel(readl(reg) & ~hwirq_mask, reg);
}

[    9.465613] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.4.7-g078c0f7c1536-dirty #37
[    9.466334] Hardware name: riscv-virtio,qemu (DT)
[    9.466692] Call Trace:
[    9.466921] [<ffffffff8000548e>] dump_backtrace+0x1c/0x24
[    9.467377] [<ffffffff80830010>] show_stack+0x2c/0x38
[    9.467811] [<ffffffff8083b1ca>] dump_stack_lvl+0x3c/0x54
[    9.468223] [<ffffffff8083b1f6>] dump_stack+0x14/0x1c
[    9.468603] [<ffffffff804e6708>] serial8250_interrupt+0xa6/0xae    //串口中断处理函数
[    9.469319] [<ffffffff80060456>] __handle_irq_event_percpu+0x54/0x142
[    9.470232] [<ffffffff800605d0>] handle_irq_event+0x3c/0x88
[    9.471057] [<ffffffff80064106>] handle_fasteoi_irq+0x9c/0x19a 
[    9.471973] [<ffffffff8005f82e>] generic_handle_domain_irq+0x1c/0x2a
[    9.472969] [<ffffffff8044b6d0>] plic_handle_irq+0x8a/0xf0     // plic中断总入口
[    9.473783] [<ffffffff8005f82e>] generic_handle_domain_irq+0x1c/0x2a
[    9.474675] [<ffffffff8044b318>] riscv_intc_irq+0x2e/0x46
[    9.475407] [<ffffffff8083bca6>] do_irq+0x50/0x84
[    9.475988] [<ffffffff80003660>] ret_from_exception+0x0/0x64   // 所有广义的异常(中断和异常)入口
[    9.476593] [<ffffffff8083c57e>] default_idle_call+0x26/0x34
[    9.477368] [<ffffffff8004a096>] do_idle+0x204/0x224 
[    9.478087] [<ffffffff8004a210>] cpu_startup_entry+0x1a/0x1c
[    9.478874] [<ffffffff8083c8d0>] kernel_init+0x0/0x10a
[    9.479617] [<ffffffff80a00672>] arch_post_acpi_subsys_init+0x0/0x18
[    9.480129] [<ffffffff80a010cc>] console_on_rootfs+0x0/0x68